Non-volatile memory devices that store or read a block of data at a time, such as a page of data, are well known in the art. For example, NAND memory devices typically can store a page, such as 4 kilobytes, of data in the device at each read/write operation. Other types of non-volatile memory devices that store or read a block of data at a time, include so called managed NAND memory devices, such as the NANDrive memory device available from Greenliant Systems, Inc. of Santa Clara Calif. In a managed NAND memory device, such as the NANDrive memory device, a controller controls the raw (or unmanaged) NAND memory device so that standard interface, such as SATA (serial ATA) can be used to interface with the NANDrive memory device. As used herein, the term “NAND memory device” shall refer to both raw as well as managed NAND memory devices.
In a NAND memory device, the non-volatile memory device can be written to or read from only in blocks of data at a time. Because of their ability to read back a block of data at a time, NAND memory devices are useful to store large amounts of data.
In the prior art, because NAND memory devices are subject to error, data has been stored in NAND memory devices along with error checking bits. Thus, one well known error checking bit that is generated from a plurality of data bits is a parity bit. Other types of error bits include Reed-Solomon error bits and other well known types. Data bits and error bits generated from the data bits are supplied to a plurality of NAND memory devices. One prior art method of storing a block of data bit is to break the block of data into a plurality of equal sub-blocks of data with each sub-block of data supplied to a physically distinct NAND memory device different from one another. The associated error bits (for the plurality of sub-blocks of data) are supplied to another physically distinct NAND memory device. Thus, all of the block of data bits and error bits are supplied to physically distinct NAND memory devices.
The sub-block of data that is supplied to each distinct NAND memory device can be stored in one of two ways. First, as the sub-block of data is received in the buffer of the NAND memory device, it is stored in a block of NAND memory cells for storage. This is wasteful because the block of storage contains only a sub-block amount of data. Alternatively, the sub-block of data can be kept in the buffer until another sub-block (from a different block of data) is received and so on, until an amount of data equal to a block is received in the buffer, in which case the entire block of data (comprising of many sub-blocks from different blocks of data) in the buffer can be stored in a block of storage. This alternative method is also not optimal because the data is kept in the buffer and there is the possibility of power failure causing loss of data, since the buffer is usually a volatile memory.
On read back, once a block of storage is read out from one of the NAND memory devices, the data read from the block of storage must be parsed to retrieve the selected sub-block of data. The plurality of sub-blocks of data associated with the select block (along with the associated error bits) are read out of the physically distinct NAND memory devices. The data from all of the data blocks are compared to the data from the error block to determine if an error occurred. In order for this method to operate correctly, in the prior art, a block of data is split into multiple sub-blocks and then with a block of error bits, reducing the size of data that is stored and read, which in turn reduces the read and write efficiency. For example, if a block of data is 4 kilobytes and is stored across 8 NAND devices. Each sub-block of data is 0.5 kilobytes and is stored in each block of a NAND device. On read-out, if 8 blocks of data or 32 kilobytes is desired, each of the eight (8) NAND devices has to be read eight times. The amount of data from each sub-block (0.5 kilobytes) from each of the eight (8) NAND devices has to assembled into a block of 4 kilobytes. However, the amount of time required to read a NAND device is due to the time required to set up the command operation, the time required to read the array of non-volatile memory cells, and the actual transfer time of 0.5 kilobytes form each NAND device. The amount of time to set up the command operation and the amount of time required to read the array are virtually the same, irrespective of the amount of data to be transferred. Since the block size of NAND devices is increasing, using the prior art method of splitting a block of data into sub-blocks and storing the sub-blocks in a block of a NAND device requires more time during the read operation.
Referring to FIG. 1 there is shown a schematic block diagram of a memory system 10 of the prior art and its attending problem in storing a plurality of blocks of data. FIG. 1 shows eight (8) blocks of data, having logical addresses of “logical address 1”, “logical address 2”, “logical address 3” etc. The memory system 10 also has eight NAND memory devices 20(a-h), shown as “Device 1”, “Device 2”, “Device 3” and “Device 8”, respectively, and a ninth NAND memory device 20i for storing, parity bits. A memory controller (not shown) controls the operation of the Devices 20(a-h) as well as the directing of the blocks of data into the various Devices 20(a-h), generating the parity bits and storing the parity bits in device 20i. In the prior art, when a block of data is received, such as the block of data having the logical address 1, the memory controller divides the block of data into eight sub-blocks and stores each sub-block into a different NAND device 20(a-h). Thus, as shown in FIG. 1, the block with logical address 1 and having a physical address A is divided into eight (8) sub-blocks with each sub-block stored in a different memory device 20(a-h). The memory controller generates a sub-block of parity bits based upon the eight sub-blocks of data from logical addresses 1 and stores the sub-block of parity bits into Device 9 20i. All of the eight (8) sub-blocks of data (nine including the sub-block of parity bits) from the data block with the logic address 1 are stored in a block of NAND device with a physical address A, albeit the blocks with physical address A are all in different memory NAND devices 20(a-i), but with the same physical address. A second block of data with logical address of 2 is stored in the same manner. The block of data is divided into eight (8) sub-blocks, but all with the physical address of B, and is stored in the NAND devices 20(a-h), with the associated parity bits to the eight (8) sub-blocks of data stored in the NAND device 20(i).
On read out, assume that the block having the logical address of logical address 3 is desired to be read, then the memory controller causes each of the NAND memory devices 20(a-h) to read the block of data at the physical addresses C associated with the logical address 3 from the non-volatile memory cells and into the respective buffer within each of the NAND memory devices 20(a-h). Thereafter, the data block having the logical address of logical address 3 is assembled based upon the eight sub-blocks of data read, and the data is compared to the parity bits from the device 20i, to ascertain whether there is any error. In addition, if any of the devices (a-h) detects an error, the block of parity bits associated with the data block having the logical address of 3 is read from the NAND memory device 20i and stored in its buffer. Then the error is corrected, and written back into the erroneous NAND memory device as well as having the corrected data supplied from the memory system 10. If there is no, error, the uncorrected data from the block having the logical address of logical address 3 is then supplied from the memory system 10.
As previously discussed, the problem with the storage of these blocks of data is that as NAND devices 20 increase in data transfer speeds and decrease in storage read latency, the read overhead dramatically reduces the performance of the storage system. This leads to increased overhead and time to read a large number of small blocks of data. Using the above as an example, if eight (8) blocks of data having logical addresses of (1-8) were desired to be read from the memory system 10, then from the foregoing discussion, it can be seen that each NAND device 20(x) must be read 8 times (even if we assume that all eight (8) memory devices 20(a-h)—including the NAND memory device 20(i)) for storing the parity bits) can be read simultaneously. Each of the eight (8) small block read operations, as discussed heretofore, requires the overhead time to set up the read operation, the time to read the array, and finally the time to transfer the data from the NAND device 20. That becomes more of a bottle neck, as NAND devices increase in array read latency and decrease in transfer time.